SpaceWire Router IP Core

The SpaceWire Router IP Core is a microcell offering a configurable and flexible solution for high data-rate routing switch functionality for on-board satellite networking. It is based on the SpaceWire protocol, defining bi-directional, full-duplex, serial data communication link, and it is compliant with the SpaceWire standard ECSS-EST-50-12C Rev.1 (SpaceWire Routing Switch specification). The SpaceWire Router IP Core features a parametrized number of SpaceWire ports, based on proprietary SpaceWire CODEC IP Core, and host-side data ports, based on asynchronous FIFO interfaces. The host data ports can be optionally equipped with AMBA AXI interface. The host-side data ports can be extended with Direct Memory Access (DMA) and standard bus interface such as AMBA AXI, to make it easier to use the IP Core within microprocessor-based systems, and it can be equipped with RMAP target commands manager in conformance with ECSS‐E‐ST‐50‐52C standard. The SpaceWire Router IP Core has been validated and prototyped in ESA project. Key features: Highly customisable to fulfil user needs Compliant with ECSS-E-ST-50-12C Rev.1 standard (SpaceWire Routing Switch specification) Up to 31 SpaceWire and/or host data (FIFO) ports Path addressing logical addressing regional addressing and multicast addressing support SpaceWire TX bit rate and link start mode programmability for each available SpaceWire port Host data ports with simple FIFO-based interface Time-Code distribution support in both slave and master mode SpaceWire links configuration/check and port addresses mapping/check via SpaceWire packets Optional support to RMAP target commands in conformance with ECSS‐E‐ST‐50‐52C standard Optional support to AMBA AXI-4 Memory Mapped interfaces backward compatible with AXI-3 specification Technology-independent VHDL IP core successfully implemented and tested on many FPGA devices for space Other information: Technologies/Applications SpaceWire Competencies: FPGA/ASIC design IP Core design Verification