CCSDS 131.2-B Receiver IP Core

The CCSDS 131.2-B Receiver IP Core is a complete solution to implement the core functions of a receiver compliant with the CCSDS 131.2-B standard: this standard has been conceived for Low Earth Observation mission with high data rate (more than 2 Gbps) and its primary application is to provide a complete solution for the implementation of a low-cost receiver based on commercial FPGAs to be used into the Ground Stations (Downlink application). The main functions covered by the IP Core include the signal processing of the I/Q digital baseband signal, carrier frequency and phase recovery, timing recovery, demodulation of all the 27 Modulation and Coding formats (ModCods) from QPSK to 8PSK and 16-, 32- and 64-APSK, and decoding based on Serially Concatenated Convolutional Codes (SCCC). In addition, the IP Core is suitable for integration into space qualified FPGA for the implementation of Uplink/Forward links application. The CCSDS 131.2-B Receiver IP Core has been developed within the framework of an ESA project. Key features: Fully compliant with CCSDS 131.2-B-1 standard Baseband I/Q signal as input frequency phase and timing recovery loops Carrier acquisition and tracking with doppler effect up to 6.5 kHz/s of doppler rate Implementation loss lower than 2 dB with respect to performances reported in CCSDS 130.1-G-1 at CER 10-4 for ModCods based on 64-APSK with AWGN Doppler and phase noise Standard interfaces for easy integration based on AXI Lite and AXI Stream standard Optional mitigation techniques to safely operate in space environment: EDAC on internal memories Dead-lock free FSM design with one-hot encoding Ground (Downlink) target applications: all the 27 ModCods in a single instantiation based on commercial FPGAs (e.g.; Intel Stratix 10; Xilinx ZynQ/Virtex UltraScale+) Space (Uplink) target applications: optimized configuration targeting FPGAs for space (e.g.; Microchip PolarFire RT; Xilinx Kintex Ultrascale XQRKU060) Coded in technology-independent highly configurable VHDL Validation on commercial Xilinx VCU118 development kit for Downlink Dynamically configurable baud rate up to 500 MBaud Other information: Technologies/Applications CCSDS 131.2-B Competencies FPGA/ASIC design IP Core design Verification Digital signal processing